Modulator providing only quantization error component to delta sigma modulator

ABSTRACT

A ΔΣ modulator modulates only an error component separated by a component separating portion. Therefore, even if the number of order of the ΔΣ modulator increases, an amplitude of an output of an integrator in the final stage does not excessively increase, and the stability of the modulator can be achieved. Since the signal component separated by the component separating portion does not pass through the ΔΣ modulator, an intensity of an input signal can be maintained as it is, and the modulator can have high precision.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a modulator employing anoversampling ΔΣ converting method, which has been widely used in A/D(Analog-to-Digital) converters and D/A (Digital-to-Analog) convertersfor an audio band or range. Particularly, the invention relates to amodulator, which can reduce suppression of an input signal in a highorder, and thereby can achieve high precision and improved stability inthis conversion method.

[0003] 2. Description of the Background Art

[0004] Modulators of an oversampling ΔΣ conversion method are now widelyused for A/D converters and D/A converters, which may be referred to as“ADCs” and “DACs” hereinafter, respectively, for the audio band. As willbe described later, the oversampling ΔΣ modulator is formed of a delayelement, an integrator, an adder and a quantizer.

[0005] Japanese Patent Laying-Open Nos. 3-22626, 11-308110, 6-53836 and2002-76902 have disclosed inventions relating to the above technology.

[0006] Japanese Patent Laying-Open No. 3-22626 has disclosed a fourth ΔΣconverter, which is formed of a primary loop and secondary loops. Anoutput F of the main loop is expressed by the following formula:

F=X(z)+(1−z ⁻¹)² ·Q ₁(z)  (1)

[0007] where X(z) represents an input signal, and Q₁(z) representsquantization noises of a first quantizer.

[0008] If the first quantizer is formed of a simple comparator, thefollowing relationship is present between its input E and output F:

F=E+Q ₁(z)  (2)

−Q ₁(z)=E−F  (3)

[0009] In the secondary loop, a quantization error −Q₁(z) is integratedaccording to secondary transfer characteristics. A quantization output Gis expressed by the following formula:

G=−Q ₁(z)+(1−z ⁻¹)² ·Q ₂(z)  (4)

[0010] where Q₂(z) expresses quantization noises of a second quantizer.

[0011] In this secondary loop, first and second differentiators arearranged downstream from the secondary quantizers, and differentiatequantization output G twice. An output H after the two differentiatingoperations is as follows:

H=−(1−z ⁻¹)² ·Q ₁(z)+(1−z ⁻¹)⁴ ·Q ₂(z)  (5)

[0012] where (1−z⁻¹) represents a transfer function of the first andsecond differentiators.

[0013] By adding this output H of the secondary loop to output F of theprimary loop, (1−z⁻¹)²·Q₁(z) in the formula (1) cancels (−(1−z¹)²·Q₁(z))in the formula (5) so that a final output Y(z) is expressed by thefollowing formula:

Y(z)=X(z)+(1−z ⁻¹)⁴ ·Q ₂(z)  (6)

[0014] In this manner, the ΔΣ converter of a quadruple-integration typeis equivalently achieved.

[0015] Japanese Patent Laying-Open No. 11-308110 has disclosed a ΔΣ-typeA/D converter, which includes a plurality of cascaded delta-sigma loopsfor noise shaving and reduction of quantization noises.

[0016] Japanese Patent Laying-Open No. 6-53836 has disclosed ananalog-to-digital converter circuit, which performs multiplication with(a≦1) by a factor multiplier, and performs restoration to an originalsize by the factor multiplier so that an input signal applied to theintegrator of the delta-sigma A/D converter loop for the correction maybe reduced.

[0017] Japanese Patent Laying-Open No. 2002-76902 has disclosed a priorart, in which a decimation filter arranged in a downstream positionremoves a noise power distributed outside an signal band.

[0018] As will be described later, an effect by modulation depends onthe number of bit of the quantizers, or the number (order) of thefeedback stages following the output of the integrator and quantizer.Thus, a higher order of the feedback stage increases the effect by themodulation if the number of bits of the quantizer is constant, and thuscan achieve more precise modulation. However, a higher order of themodulator may excessively increase an amplitude of an output of theintegrator in the final stage, resulting in a problem that largeoscillation occurs.

[0019] In any one of the foregoing prior arts, since an original signalis provided to the modulator of the primary loop, the foregoing problemscannot be overcome.

SUMMARY OF THE INVENTION

[0020] An object of the invention is to provide a modulator, which canimprove stability and precision.

[0021] A modulator according to an aspect of the invention is amodulator using a delta-sigma conversion method, and includes acomponent separating portion separating a signal component and an errorcomponent of an input signal from each other, a delta-sigma modulatormodulating the error component separated by the component separatingportion, and an output operating portion operating the signal componentseparated by the component separating portion and the error componentmodulated by the delta-sigma modulator.

[0022] Since the delta-sigma modulator modulates only the errorcomponent separated by the component separating portion, an amplitude ofan output of an integrator in a final stage does not increaseexcessively even if the number of order of the delta-sigma modulator isincreased. Therefore, stability of the modulator can be achieved.Further, the signal component separated by the component separatingportion does not pass through the delta-sigma modulator so that theintensity of the input signal can be maintained as it is, and highprecision can be achieved in the modulator.

[0023] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIGS. 1A and 1B are block diagrams showing an example of astructure of an oversampling ΔΣ modulator.

[0025]FIG. 2 illustrates a concept of modulation of quantization noisesin the ΔΣ modulator.

[0026]FIG. 3 illustrates a general method for overcoming a problemoccurring in the ΔΣ modulator shown in FIG. 1.

[0027]FIG. 4 is a block diagram showing a schematic structure of amodulator of a first embodiment of the invention.

[0028] FIGS. 5 to 12 are block diagrams showing structures of modulatorsof second to ninth embodiments of the invention, respectively.

[0029]FIG. 13 is a block diagram showing a structure of a ΔΣ D/Aconverter according to a tenth embodiment of the invention.

[0030]FIG. 14 is a block diagram showing a structure of a ΔΣ A/Dconverter according to an eleventh embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031]FIGS. 1A and 1B are block diagrams showing by way of example astructure of an oversampling ΔΣ modulator. As shown in FIG. 1A, the ΔΣmodulator includes adders 11 and 13, integrators 12 and 14, a one-bitquantizer 15 and a delay element 16. As shown in FIG. 1B, each ofintegrators 12 and 14 includes an-adder 17 and a delay element 18.

[0032]FIG. 2 illustrates a concept of modulation of quantization noisesin the ΔΣ modulator. The quantization noises occurring in quantizer 15are subjected to modulation so that the quantization noises within aband are extruded to a high-frequency band. Thereby, even a quantizer ofa small number of bits can achieve a D/A or A/D converter with highprecision. Thus, large quantization errors occurring in the quantizer ofthe small number of bits are extruded to a high band so that the noiseswithin the band (low range) is reduced in amount, and the precision ofthe ΔΣ modulator is improved.

[0033]FIG. 1A shows the second-order modulator. However, increase innumber of the order of the modulator may excessively increase anamplitude of an output of an integrator in a final stage so thatoscillation is liable to occur, resulting in deterioration of stability.

[0034]FIG. 3 illustrates a general manner for overcoming a problemarising in the ΔΣ modulator shown in FIGS. 1A and 1B. This high-order(nth) ΔΣ modulator includes an attenuator 21, adders 22-1-22-n,integrators 23-1-23-n, a quantizer 24 and a delay element 25.

[0035] In FIG. 3, attenuator 21 having a coefficient not exceeding oneis arranged before the high-order (nth) ΔΣ modulator for preventing anexcessive amplitude of the output of the integrator in the final stage.Output signal Y can be expressed by the following formula:

Y=bX+(1−z ⁻¹)^(n) ·Q  (7)

[0036] where X represents an input signal, Q represents an quantizationerror and b represents a coefficient of attenuator 21.

[0037] As described above, the arrangement of attenuator 21 can improvethe stability, but restricts the output amplitude. This results in aproblem that the precision to be originally achieved by the modulatorcannot be achieved. As the order of the modulator becomes higher,attenuator 21 has a coefficient of a lower value, which makes the aboveproblem more remarkable.

[0038] (First Embodiment)

[0039]FIG. 4 is a block diagram showing a schematic structure of amodulator of a first embodiment of the invention. This modulatorincludes a component separating portion 31, which separates a quantizedsignal component (X+Q) and a quantization error component (Q) of theinput signal (X) from each other, a ΔΣ modulator 32 modulating onlyquantization error component (Q), and an output operating portion 33performing an arithmetic operation on quantized signal component (X+Q)and the output of ΔΣ modulator 32.

[0040] ΔΣ modulator 32 modulates only the error component. Therefore,even if the order of ΔΣ modulator 32 becomes high, the amplitude of theoutput of the final integrator does not excessively increase, and thestability of the modulator can be achieved. Further, output operatingportion 33 performs an operation on quantized signal component (X+Q),which is separated by component separating portion 31, and the output ofΔΣ modulator 32 so that the quantization error component Q is cancelled.Since the input of the modulator is quantization error component Q, theamplitude is small, and increase in output of the final integrator canbe prevented. Therefore, it is not necessary to arrange the attenuatorbefore the modulator so that lowering of the signal intensity of outputsignal Y can be prevented, and the precision of the modulator can beimproved.

[0041] Specific examples of the modulator according to the firstembodiment will now be described. Second to fifth embodiments to bedescribed below relate to digital ΔΣ modulators, respectively, and sixthto ninth embodiments relate to analog ΔΣ modulators, respectively.

[0042] (Second Embodiment)

[0043]FIG. 5 is a block diagram showing a structure of a modulatoraccording to a second embodiment of the invention. This modulatorincludes a quantizer 41 of one bit for quantizing a digital input signalX, an adder 42 adding input signal X to a quantized signal component(−(X+Q)) provided from quantizer 41, a single-stage ΔΣ modulator 43, andan adder 44 adding quantized signal component (X+Q) provided fromquantizer 41 to the output signal of single-stage ΔΣ modulator 43.

[0044] Single-stage ΔΣ modulator 43 is an nth ΔΣ modulator includingadders 45-1-45-n, integrators 46-1-46-n, a quantizer 47 and a delayelement, 48. The output of quantizer 47 is delayed by delay element 48,and then negative feedback is performed to provide it to integrators46-1-46-n by adders 45-1-45-n.

[0045] Single-stage ΔΣ modulator 43 provides an output of(−Q+(1−z⁻¹)^(n)·Q₂). Therefore, output signal Y is expressed by thefollowing formula:

Y=X+(1−z ⁻¹)^(n) ·Q ₂  (8)

[0046] where Q₂ represents an error component occurring in single-stageΔΣ modulator 43.

[0047] According to the modulator of the embodiment, as alreadydescribed, adder 42 adds input signal X to quantized signal component(−(X+Q)) provided from quantizer 41, and supplies only quantizationerror component (−Q) to single-stage ΔΣ modulator 43. Therefore, theinput of single-stage ΔΣ modulator 43 is substantially equal to half theoriginal signal (X), and the stability of the modulator can be improved.

[0048] Quantized signal component (X+Q) provided from quantizer 41 isdirectly supplied to adder 44 without passing through single-stage ΔΣmodulator 43. Therefore, the intensity of input signal X can bemaintained as it is, and the precision of the modulator can be improved.

[0049] This embodiment has been described in connection with the one-bitfeedback method. However, the modulator may be of a multibit type, andanother conversion method such as a feed-forward architecture may beemployed. These type and method can achieve effects similar to thosealready described.

[0050] (Third Embodiment)

[0051]FIG. 6 is a block diagram showing a structure of a modulator of athird embodiment of the invention. This modulator differs from themodulator of the second embodiment shown in FIG. 5 only in thatquantizer 41 is replaced with a multibit quantizer 45. Therefore,description of the same structures and functions is not repeated.

[0052] Multibit quantizer 45 quantizes input signal X to provide aquantized signal component (X+Q_(m)). Adder 42 adds digital input signalX to quantized signal component (−(X+Q_(m))) provided from multibitquantizer 45, and provides only quantization error component (−Q_(m)) tosingle-stage ΔΣ modulator 43.

[0053] Single-stage ΔΣ modulator 43 provides an output of(−Q_(m)+(1−z⁻¹)^(n)·Q₂). Output signal Y is the same as that expressedby the formula (8) in the first embodiment already described.

[0054] According to the modulator of this the embodiment, as describedabove, adder 42 adds input signal X to quantized signal component(−(X+Q_(m))) provided from multibit quantizer 45, and provides onlyquantization error component (−Q_(m)) to single-stage ΔΣ modulator 43.Since quantization error Q_(m) can be smaller than quantization error Qin the second embodiment, the input of single-stage ΔΣ modulator 43 canbe further reduced so that the stability of the modulator can be furtherimproved as compared with the modulator of the second embodiment.

[0055] (Fourth Embodiment)

[0056]FIG. 7 is a block diagram showing a structure of a modulator of afourth embodiment of the invention. This modulator differs from themodulator of the second embodiment shown in FIG. 5 only in that anattenuator 46 having a coefficient of α smaller than one is arranged ina stage preceding single-stage ΔΣ modulator 43, and an attenuator 47having a coefficient of 1/α is arranged in a stage followingsingle-stage ΔΣ modulator 43. Therefore, description of the samestructures and functions is not repeated.

[0057] As the number n of order of single-stage ΔΣ modulator 43 isincreased, the amplitude of output of the integrator in the final stageincreases, and oscillation may occur, even if an input amplitude ofsingle-stage ΔΣ modulator 43 decreases. For preventing it, attenuator 46is added to a position preceding single-stage ΔΣ modulator 43.

[0058] Owing to attenuator 46 having coefficient of α, single-stage ΔΣmodulator 43 provides an output of (−αQ+(1−z⁻¹)^(n)·Q₂). Therefore,output signal Y is expressed by the following formula:

Y=X+(1/α)×(1−z ⁻¹)^(n) *Q ₂  (9)

[0059] According to the modulator of the embodiment, as described above,attenuator 46 having a coefficient of α is added to the positionpreceding single-stage ΔΣ modulator 43, and attenuator 47 having acoefficient of (1/α) is added to the position following single-stage ΔΣmodulator 43. Therefore, it is possible to reduce an amplitude of theoutput of integrator 46-n in the final stage of single-stage ΔΣmodulator 43, and the oscillation of integrator 46-n can be prevented.Thus, it is possible to ensure the intended stability of the modulatorwhile ensuring the intended amplitude of the modulator. The coefficientof α of attenuator 46 may be larger than the coefficient of attenuator21 shown in FIG. 3 so that attenuator 46 may perform attenuation to asmaller extent.

[0060] (Fifth Embodiment)

[0061]FIG. 8 is a block diagram showing a structure of a modulator of afifth embodiment of the invention. This modulator differs from themodulator of the second embodiment shown in FIG. 5 only in thatsingle-stage ΔΣ modulator 43 is replaced with a cascade ΔΣ modulator 50.Therefore, description of the same structures and functions is notrepeated.

[0062] Cascade ΔΣ modulator 50 is formed of cascaded single-stage ΔΣmodulators, and includes adders 51, 53, 57, 58, 60 and 65, integrators52, 54, 59 and 61, quantizers 55 and 62, delay elements 56 and 63, and adifferentiator 64 performing differentiation twice.

[0063] An output Y1 of quantizer 55 is expressed by the followingformula:

Y 1=A+Q ₂ =−Q+(1−z ⁻¹)² ·Q ₂  (10)

[0064] where A represents an input of quantizer 55, and Q₂ represents aquantization error of quantizer 55.

[0065] Adder 57 adds input A of quantizer 55 to an output (−(A+Q₂)) ofquantizer 55 to provide quantization error (−Q₂) of quantizer 55.

[0066] An output of quantizer 62 is expressed by (−Q₂+(1−z¹)²·Q_(n)),where Q_(n) represents a quantization error of quantizer 62. Also, anoutput of differentiator 64 is expressed by (−Q₂·(1−z¹)²+(1−z¹)⁴·Q_(n)).Therefore, adder 65 provides an output of (−Q₂+(1−z⁻¹)⁴·Q_(n)).

[0067] By the provision of the cascade ΔΣ modulator described above,quantization errors (Q₂, Q₃, . . . ) occurring in the quantizers exceptfor that in the final stage can be removed by addition of those of theneighboring stages. Therefore, the item of (1/α) in the formula (9) ofthe fourth embodiment already described can be removed.

[0068] According to the modulator of this embodiment, as describedabove, cascade ΔΣ modulator 50 is used to modulate quantization errorcomponent (−Q). Therefore, the amplitude of the output of integrator 61in the final stage of cascade ΔΣ modulator 50 can be reduced withoutusing an attenuator, and the oscillation in integrator 61 can beprevented. Thus, the stability of the modulator can be ensured whileensuring the amplitude of the modulator.

[0069] This embodiment has been described in connection with the casewhere two one-bit secondary ΔΣ modulators of the feedback type arecascaded. However, the number of cascaded stages may be increased,and/or a multibit quantizer may be employed as the quantizer in thefinal stage so that a modulator having higher precision can be achieved.Further, the conversion method of the modulator may employ another typesuch as a feed-forward type. In these cases, effects similar to thosealready described can be achieved.

[0070] (Sixth Embodiment)

[0071]FIG. 9 is a block diagram showing a structure of a modulatoraccording to a sixth embodiment of the invention. This modulatorincludes quantizer 41 (A/D converter) of one bit for quantizing analoginput signal X, a D/A converter 71 converting quantized signal component(X+Q) provided from quantizer 41 to an analog signal, adder 42 addinginput signal X to signal component (−(X+Q)) provided from D/A converter71, a single-stage ΔΣ modulator 70, and adder 44 adding quantized signalcomponent (X+Q) provided from quantizer 41 to the output signal ofsingle-stage ΔΣ modulator 70.

[0072] Single-stage ΔΣ modulator 70 is an nth ΔΣ modulator includingadders 45-1-45-n, integrators 46-1-46-n, quantizer 47, delay element 48and a D/A converter 49 converting the output signal of quantizer 47 toan analog signal. The output of D/A converter 49 is delayed by delayelement 48, and then negative feedback is performed to provide it tointegrators 46-1-46-n by adders 45-1-45-n.

[0073] Single-stage ΔΣ modulator 70 provides an output of(−Q+(1−z⁻¹)^(n)·Q₂). Therefore, output signal Y is expressed by theforegoing formula (8).

[0074] According to the modulator of the embodiment, as alreadydescribed, adder 42 adds analog input signal X to signal component(−(X+Q)) provided from D/A converter 71, and supplies only errorcomponent (−Q) to single-stage ΔΣ modulator 70. Therefore, the input ofsingle-stage ΔΣ modulator 70 is substantially equal to half the originalsignal (X), and the stability of the modulator can be improved.

[0075] Quantized signal component (X+Q) provided from quantizer 41 isdirectly supplied to adder 44 without passing through single-stage ΔΣmodulator 70. Therefore, the intensity of input signal X can bemaintained as it is, and the precision of the modulator can be improved.

[0076] The embodiment of the invention has been described in connectionwith the one-bit feedback method. However, the modulator may be of amultibit type, and another conversion method such as a feed-forwardarchitecture may be employed. These type and method can achieve effectssimilar to those already described.

[0077] (Seventh Embodiment)

[0078]FIG. 10 is a block diagram showing a structure of a modulator of aseventh embodiment of the invention. This modulator differs from themodulator of the sixth embodiment shown in FIG. 9 only in that quantizer41 is replaced with multibit quantizer (D/A converter) 45. Therefore,description of the same structures and functions is not repeated.

[0079] Multibit quantizer 45 quantizes analog input signal X to providesignal component (X+Q_(m)). Adder 42 adds analog input signal X tosignal component (−(X+Q_(m))) provided from D/A converter 71, andprovides only error component (−Q_(m)) to single-stage ΔΣ modulator 43.

[0080] Single-stage ΔΣ modulator 43 provides an output of(−Q_(m)+(1−z⁻¹)^(n)·Q₂). Output signal Y is the same as that expressedby the formula (8) in the first embodiment already described.

[0081] According to the modulator of this embodiment, as describedabove, adder 42 adds input signal X to signal component (−(X+Q_(m)))provided from D/A converter 71, and provides only error component(−Q_(m)) to single-stage ΔΣ modulator 70. Since quantization error Q_(m)can be smaller than quantization error Q in the sixth embodiment, theinput of single-stage ΔΣ modulator 70 can be further reduced so that thestability of the modulator can be further improved as compared with themodulator of the sixth embodiment.

[0082] (Eighth Embodiment)

[0083]FIG. 11 is a block diagram showing a structure of a modulator ofan eighth embodiment of the invention. This modulator differs from themodulator of the sixth embodiment shown in FIG. 9 only in thatattenuator 46 having a coefficient of α smaller than one is arranged ina stage preceding single-stage ΔΣ modulator 70, and attenuator 47 havinga coefficient of 1/α is arranged in a stage following single-stage ΔΣmodulator 70. Therefore, description of the same structures andfunctions is not repeated.

[0084] As the number n of order of single-stage ΔΣ modulator 70 isincreased, the amplitude of output of the integrator in the final stageincreases, and oscillation may occur, even if an input amplitude ofsingle-stage ΔΣ modulator 70 decreases. For preventing it, attenuator 46is added to a position preceding single-stage ΔΣ modulator 70.

[0085] Owing to attenuator 46 having coefficient of α, single-stage ΔΣmodulator 70 provides an output of (−αQ+(1−z⁻¹)^(n)·Q₂). Therefore,output signal Y is expressed by the formula (9) already described.

[0086] According to the modulator of the embodiment, as described above,attenuator 46 having a coefficient of α is added to the positionpreceding single-stage ΔΣ modulator 70, and attenuator 47 having acoefficient of (1/α) is added to the position following single-stage ΔΣmodulator 70. Therefore, it is possible to reduce an amplitude of theoutput of integrator 46-n in the final stage of single-stage ΔΣmodulator 70, and the oscillation of integrator 46-n can be prevented.Thus, it is possible to ensure the intended stability of the modulatorwhile ensuring the intended amplitude of the modulator. The coefficientof α of attenuator 46 may be larger than the coefficient of attenuator21 shown in FIG. 3 so that attenuator 46 may perform attenuation to asmaller extent.

[0087] (Ninth Embodiment)

[0088]FIG. 12 is a block diagram showing a structure of a modulator of aninth embodiment of the invention. This modulator differs from themodulator of the sixth embodiment shown in FIG. 9 only in thatsingle-stage ΔΣ modulator 70 is replaced with a cascade ΔΣ modulator 80.Therefore, description of the same structures and functions is notrepeated.

[0089] Cascade ΔΣ modulator 80 is formed of cascaded single-stage ΔΣmodulators, and includes adders 51, 53, 57, 58, 60 and 65, integrators52, 54, 59 and 61, quantizers 55 and 62, delay elements 56 and 63, adifferentiator 64 performing differentiation twice, and D/A converters66 and 67.

[0090] Output Y1 of quantizer 55 is expressed by the foregoing formula(10), where A represents an input of quantizer 55, and Q₂ represents aquantization error of quantizer 55.

[0091] Adder 57 adds input A of quantizer 55 to an output (−(A+Q₂)) ofD/A converter 66 to provide quantization error (−Q₂) of quantizer 55.

[0092] An output of quantizer 62 is expressed by (−Q₂+(1−z⁻¹)²·Q_(n))where Q_(n) represents a quantization error of quantizer 62. Also, anoutput of differentiator 64 is expressed by(−Q₂*(1−z¹)²+(1−z⁻¹)⁴·Q_(n)). Therefore, adder 65 provides an output of(−Q₂+(1−z¹)⁴·Q_(n)).

[0093] By the provision of the cascade ΔΣ modulator described above,quantization errors (Q₂, Q₃, . . . ) occurring in the quantizers exceptfor that in the final stage can be removed by addition of those of theneighboring stages. Therefore, the item of (1/α) in the formula (9) ofthe fourth embodiment already described can be removed According to themodulator of this embodiment, as described above, cascade ΔΣ modulator80 is used to modulate error component (−Q). Therefore, the amplitude ofthe output of integrator 61 in the final stage of cascade ΔΣ modulator80 can be reduced without using an attenuator, and the oscillation inintegrator 61 can be prevented. Thus, the stability of the modulator canbe ensured while ensuring the amplitude of the modulator.

[0094] This embodiment has been described in connection with the casewhere two one-bit secondary ΔΣ modulators of the feedback type arecascaded. However, the number of cascaded stages may be increased,and/or a multibit quantizer may be employed as the quantizer in thefinal stage so that a modulator having higher precision can be achieved.Further, the conversion method of the modulator may employ another typesuch as a feed-forward type. In these cases, effects similar to thosealready described can be achieved.

[0095] (Tenth Embodiment)

[0096]FIG. 13 is a block diagram showing a structure of a ΔΣ D/Aconverter of a tenth embodiment of the invention. This ΔΣ D/A converterincludes an interpolation filter 91, a digital ΔΣ modulator 92, areconstruction D/A converter 93 and an analog filter (low-pass filter)94. Reconstruction D/A converter 93 and analog filter 94 may becollectively referred to as an “analog filter”.

[0097] Digital ΔΣ modulator 92 modulates digital input signal X, whichis already subjected to interpolation by interpolation filter 91.Reconstruction D/A converter 93 and analog filter 94 convert digitaloutput signal Y of digital ΔΣ modulator 92 to an analog signal.

[0098] Digital ΔΣ modulator 92 is the same as one of the modulators inthe second to fifth embodiments already described. Therefore, it ispossible to provide the ΔΣ D/A converter achieving the effects alreadydescribed in connection with the second to fifth embodiments.

[0099] (Eleventh Embodiment}

[0100]FIG. 14 is a block diagram showing a structure of a ΔΣ A/Dconverter in an eleventh embodiment of the invention. This ΔΣ A/Dconverter includes an analog ΔΣ modulator 95 and a decimation filter 96.Decimation filter 96 converts the output signal, which is alreadymodulated by analog ΔΣ modulator 95, to multibit digital data, andperforms down-sampling to achieve an intended sample rate.

[0101] Analog ΔΣ modulator 95 is the same as one of those in the sixthto ninth embodiments already described. Therefore, it is possible toprovide the ΔΣ A/D converter achieving the effects already described inconnection with the sixth to ninth embodiments.

[0102] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A modulator using a delta-sigma conversionmethod, and comprising: component separating unit separating a signalcomponent and an error component of an input signal from each other;delta-sigma modulator modulating the error component separated by saidcomponent separating unit; and output operating unit operating thesignal component separated by said component separating unit and theerror component modulated by said delta-sigma modulator.
 2. Themodulator according to claim 1, wherein said component separating unitincludes a first quantizer quantizing a digital input signal, and anadder adding said digital input signal to said signal component providedfrom said first quantizer.
 3. The modulator according to claim 2,wherein said delta-sigma modulator includes: a plurality of integrators,a second quantizer quantizing an output of the integrator in the finalstage, and a delay element delaying an output of said second quantizerto perform negative feedback by sending the delayed output to saidplurality of integrators.
 4. The modulator according to claim 2, whereinsaid delta-sigma modulator includes a plurality of single-stagedelta-sigma modulators each including: a plurality of integrators, asecond quantizer quantizing an output of the integrator in the finalstage, and a delay element delaying an output of said second quantizer,and performing negative feedback by sending the delayed output to saidplurality of integrators; and said plurality of single-stage delta-sigmamodulators are cascaded.
 5. The modulator according to claim 2, furthercomprising: an attenuator connected between said adder and saiddelta-sigma modulator, and having a coefficient smaller than one.
 6. Themodulator according to claim 1, wherein said component separating unitincludes: a multibit quantizer quantizing a digital input signal toprovide a multibit form, and an adder adding said digital input signalto said signal component provided from said multibit quantizer.
 7. Themodulator according to claim 1, wherein said component separating unitincludes: a first quantizer quantizing an analog input signal, a firstdigital-to-analog converter converting said signal component providedfrom said first quantizer to an analog signal, and an adder adding saidanalog input signal to said analog signal provided from said firstdigital-to-analog converter.
 8. The modulator according to claim 7,wherein said delta-sigma modulator includes: a plurality of integrators,a second quantizer quantizing an output of the integrator in the finalstage, a second digital-to-analog converter converting an output of saidsecond quantizer to an analog signal, and a delay element delaying theanalog signal provided from said second digital-to-analog converter, andperforming negative feedback by sending the delayed analog signal tosaid plurality of integrators.
 9. The modulator according to claim 7,wherein said delta-sigma modulator includes a plurality of single-stagedelta-sigma modulators each including: a plurality of integrators, asecond quantizer quantizing an output of the integrator in the finalstage, a second digital-to-analog converter converting an output of saidsecond quantizer to an analog signal, and a delay element delaying theanalog signal provided from said second digital-to-analog converter, andperforming negative feedback by sending the delayed analog signal tosaid plurality of integrators; and said plurality of single-stagedelta-sigma modulators are cascaded.
 10. The modulator according toclaim 7, further comprising: an attenuator connected between said adderand said delta-sigma modulator, and having a coefficient smaller thanone.
 11. The modulator according to claim 1, wherein said componentseparating unit includes: a multibit quantizer quantizing an analoginput signal to provide a multibit form, a digital-to-analog converterconverting said signal component provided from said multibit quantizerto an analog signal, and an adder adding said analog input signal to theanalog signal provided from said digital-to-analog converter.